1. Scope of the Invention
The invention relates to logic translators and decoders, and specifically to a combined ECL-to-TTL translator and decoder circuit.
2. Description of the Prior Art
TTL (transistor-transistor logic) and ECL (emitter coupled logic) are two popular logic families in use today. Many manufacturers of integrated circuits offer an enormous variety of circuit functions in both families.
FIG. 1 shows the ranges of voltages that correspond to the logic states (HIGH and LOW) for the TTL and ECL digital logic families. The cross-hatched area above each voltage line shows the specified range of output voltages that a logic LOW or HIGH is guaranteed to fall within, with the pair of arrows indicating typical output values (LOW, HIGH) encountered in practice. The cross-hatched area below each voltage line shows the range of input voltages that are guaranteed to be interpreted as LOW or HIGH at an input line, with the arrow indicating the typical logic threshold voltage, i.e., the dividing line between LOW and HIGH. In both cases, a logic HIGH is more positive than a logic LOW.
TTL is a popular saturating logic family characterized by high speed and low power dissipation. TTL integrated circuits are extremely versatile, and they are small, economical, and reliable. Such ICs include a wide variety of gate circuits and flip flops in small-scale-integration (SSI). In addition, medium-scale-integration (MSI) ICs consist of decoders, memories, adders, counters, shift registers, multiplexers, and many others. These gates and functional networks provide for simplified design implementation.
A special form of TTL that achieves a very high speed of operation is Schottky TTL. Low propagation delay is obtained by preventing the transistors from operating in the saturation mode.
ECL, also known as current-mode logic, is a popular non-saturating logic family characterized with a small voltage swing as shown in FIG. 1. ECL is currently the fastest form of logic since the active devices within it are arranged to operate out of saturation. In addition to avoiding stored charge by this means, ECL is made even faster since the logic swings are relatively small (about 0.8 V). Thus, the time required for charging and discharging the various load and parasitic capacitances is quite short.
Both ECL and TTL logic circuits are in wide-spread use today. The ECL and TTL circuits are incompatible with one another, however, due to the differences in logic voltage levels, and hence cannot be connected directly to one another. When an ECL circuit must communicate with a TTL circuit, therefore, a circuit known as an ECL-to-TTL translator must interface the circuits.
Manufacturers commonly design logic gates and medium-scale-integrated circuits with a built-in ECL-to-TTL translator such that the circuit accepts ECL logic signals at its inputs and provides TTL logic signals at its outputs. FIG. 2 illustrates a circuit configured as a 2-by-4 decoder which accepts ECL logic input signals and provides decoded TTL logic output signals ECL input line A is connected to an ECL input buffer 10, and ECL input line B is connected to an ECL input buffer 11. ECL input buffer 10 provides output signals at the lines labelled buffered lines A and A and ECL input buffer 11 provides output signals at the lines labelled buffered lines B and B During operation, when an ECL input signal at ECL input line A is logic HIGH at a voltage -V.sub.be (where -V.sub.be .congruent.-0.9 volts), an output signal on buffered line A is at a voltage of approximately -V.sub.be and an output signal on buffered line A is at a voltage of approximately -3V.sub.be volts. When ECL input line A is logic LOW at -2V.sub.be, the output signal on buffered line A is at a voltage of approximately -3V.sub.be and the output signal on buffered line A is at a voltage of approximately -V.sub.be.
ECL input buffer 11 operates similarly. When an ECL signal at ECL input line B is logic HIGH at -V.sub.be volts, a signal on buffered line B is at approximately -V.sub.be volts and a signal on buffered line B is at approximately -3V.sub.be volts. When the signal at input line B is logic LOW at -2V.sub.be volts, the signal on buffered line B is at approximately -3V.sub.be volts and the signal on buffered line B is at approximately -V.sub.be volts.
Buffered lines A and A of ECL input buffer 10 are connected to a translator circuit 13 and to a translator circuit 14. Similarly, buffered lines B and B of ECL input buffer 11 are connected to a translator circuit 15 and to a translator circuit 16. Translator circuits 13-16 provide TTL output signals at TTL lines A, A B, and B which are TTL logic equivalents of the ECL input signals at ECL input lines A and B. For example, when ECL input line A is logic HIGH and ECL input line B is logic LOW, then TTL line A is logic HIGH, TTL line A is logic LOW, TTL line B is logic LOW, and TTL line B is logic HIGH.
TTL lines A, A B, and B of TTL translator circuits 13-16 are connected to NOR gates 17, 18, 19, and 20. Thus, the overall circuit of FIG. 2 implements a two-by-four decoder which accepts ECL input signals and provides decoded TTL output signals.
Translator circuit 13 includes P-channel FETs 13a and 13b and N-channel FETs 13c and 13d. N-channel FETs 13c and 13d are configured as a current mirror, and thus current I.sub.b can flow only when current I.sub.a flows. FETs 13a and 13b are controlled by the signals at buffered lines A and A Translator circuits 14-16 are arranged similarly. However, the connections from the buffered lines to the gates of each P-channel FET varies for each translator circuit.
When ECL input line A is logic HIGH, P-channel FETs 13a and 14b are biased OFF while P-channel FETs 13b and 14a are biased ON. TTL output line A is thus LOW and TTL output line A is HIGH. Similarly, when ECL input line B is logic HIGH, P-channel FETs 15a and 16b are biased OFF and P-channel FETs 15b and 16a are biased ON. When FET 14a is biased ON, current I.sub.a flows through FET 14a and FET 14c. Similarly, when FET 16a is biased ON, current I.sub.a flows through FET 16a and FET 16c. Appreciable power is consequently dissipated in translator circuits 14 and 16. Appreciable power is not dissipated in translator circuits 13 and 15 when FETs 13a and 15a are OFF since current I.sub.a is approximately zero and therefore current I.sub.b is approximately zero.
When ECL input line A goes LOW, thus turning on FET 13a and turning off FET 14a, the voltage at TTL output line A goes HIGH and the voltage at TTL output line A goes LOW. In addition, when ECL input line B goes LOW, FET 15a turns ON and FET 16a turns OFF. Hence, when ECL input lines A and B are both LOW, appreciable power is dissipated in translator circuits 13 and 15.
For the circuit of FIG. 2, it is apparent that for any given ECL input signal combination, exactly two of the P-channel FETs 13a, 14a, 15a, and 16a are biased ON which thus allows current I.sub.a to flow. Consequently, appreciable power is dissipated in exactly two of the translator circuits 13-16 for any given ECL input combination.